1. Field
Embodiments of the inventive concepts relate to a precharge control signal generator, and more particularly, to a precharge control signal generator included in a memory device.
2. Description of Related Art
In order to read data stored in a flash memory cell, a corresponding bit line is precharged to a predetermined voltage level through a precharge pulse, and then a determination is made as to whether the cell is turned on or off is detected by dropping the level of the bit line using a cell current. Here, an On cell corresponds to a data level of 1, and an Off cell corresponds to data level of 0. The tendency and variation of the precharge pulse according to the manner in which the pulse is applied can have a direct effect on read rate. In some cases, when a large amount of bit line leakage current is incurred, an Off cell failure can occur, in which case an Off cell may be misread as an On cell. When data are incorrectly determined, product reliability can be adversely affected.
Specifically, with the continuing trend toward further cell integration, the bit line leakage current of the Off cell can be relatively increased at high temperature operation, and thus, the Off cell failure rate can be increased.
In a conventional method, in order to mitigate or prevent the Off cell failure, the duration of the precharge signal has been controlled. When the precharge time was lengthened to meet desired Off cell detection characteristics, the lengthened precharge time can lead to over-precharging in certain On cells; also, lengthening the precharge time amounts to a decrease in read rate due to the amount of time needed for an unnecessary precharge. Further, since a bit line precharge characteristic can be degraded at a specific location by a difference in the cell characteristics due to variations in manufacturing processes, the read rate may become compromised in order to secure the precharge time for the degraded cell.